1 of 9 010700 features warns processor of an impending power failure provides time for an orderly shutdown prevents processor from destroying nonvolatile memory during power transients automatically restarts processor after power is restored suitable for linear or switching power supplies adjusts to hold time of the power supply supplies necessary signals for processor interface accurate 5% or 10% v cc monitoring replaces power-up reset circuitry no external capacitors required optional 16-pin soic surface-mount package pin assignment pin description in - input mode - selects input pin characteristics tol - selects 5% or 10% v cc detect gnd - ground rst - reset (active high) rst - reset (acti ve low, open drain) nmi - non-maskable interrupt v cc - +5v supply nc - no connections description the ds1231 power monitor chip uses a precise temperature-compensated reference circuit which provides an orderly shutdown and an automatic restart of a processor-based system. a signal warning of an impending power failure is generated well before regulated dc voltages go out of specification by monitoring high voltage inputs to the power supply regulators. if line isolation is required a ul-approved opto-isolator can be directly interfaced to the ds1231. the time for processor shutdown is directly proportional to the available hold-up time of the power supply. just before the hold-up time is exhausted, the power monitor unconditionally halts the processor to prevent spurious cycles by enabling reset as ds1231/s power monitor chip www.dalsemi.com ds1231 8-pin dip (300-mil) see mech. drawings section in mode tol gnd vcc nmi rst 1 2 3 4 8 7 6 5 rst ds1231s 16-pin soic (300-mil) see mech. drawings section nc in nc mode nc tol nc gnd nc vcc nc nmi nc rst nc rst 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8
ds1231/s 2 of 9 v cc falls below a selectable 5 or 10 percent threshold. when power returns, the processor is held inactive until well after power conditions have stabilized, safeguarding any nonvolatile memory in the system from inadvertent data changes. operation the ds1231 power monitor detects out-of-tolerance power supply conditions and warns a processor- based system of impending power failure. the main elements of the ds1231 are illustrated in figure 1. as shown, the ds1231 actually has two comparators, one for monitoring the input (pin 1) and one for monitoring v cc (pin 8). the v cc comparator outputs the signals rst (pin 5) and rst (pin 6) when v cc falls below a preset trip level as defined by tol (pin 3). when tol is connected to ground, the rst and rst signals will become active as v cc goes below 4.75 volts. when tol is connected to v cc , the rst and rst signals become active as v cc goes below 4.5 volts. the rst and rst signals are excellent control signals for a microprocessor, as processing is stopped at the last possible moments of valid v cc . on power-up, rst and rst are kept active for a minimum of 150 ms to allow the power supply to stabilize (see figure 2). the comparator monitoring the input pin produces the nmi signal (pin 7) when the input threshold voltage (v tp ) falls to a level as determined by mode (pin 2). when the mode pin is connected to v cc , detection occurs at v tp -. in this mode pin 1 is an extremely high impedance input allowing for a simple resistor voltage divider network to interface with high voltage signals. when the mode pin is connected to ground, detection occurs at v tp +. in this mode pin 1 sources 30 m a of current allowing for connection to switched inputs, such as a ul-approved opto-isolator. the flexibility of the input pin allows for detection of power loss at the earliest point in a power supply system, maximizing the amount of time allotted between nmi and rst . on power-up, nmi is released as soon as the input threshold voltage (v tp ) is achieved and v cc is within nominal limits. in both modes of operation the input pin has hysteresis for noise immunity (figure 3). application - mode pin connected to v cc when the mode pin is connected to v cc , pin 1 is a high impedance input. the voltage sense point and the level of voltage at the sense point are dependent upon the application (figure 4). the sense point may be developed from the ac power line by rectifying and filtering the ac. alternatively, a dc voltage level may be selected which is closer to the ac power input than the regulated +5-volt supply, so that ample time is provided for warning before regulation is lost. proper operation of the ds1231 requires a maximum voltage of 5 volts at the input (pin 1), which must be derived from the maximum voltage at the sense point. this is accomplished with a simple voltage divider network of r1 and r2. since the in trip point v tp - is 2.3 volts (using the -20 device), and the maximum allowable voltage on pin 1 is 5 volts, the dynamic range of voltage at the sense point is set by the ratio of 2.3/5.0=.46 min. this ratio determines the maximum deviation between the maximum voltage at the sense point and the actual voltage which will generate nmi . having established the desired ratio, and confirming that the ratio is greater than .46 and less than 1, the proper values for r1 and r2 can be determined by the equation as shown in figure 4. a simple approach to solving this equation is to select a value for r2 which is high enough impedance to keep power consumption low, and solve for r1. figure 5 illustrates how the ds1231 can be interfaced to the ac power line when the mode pin is connected to v cc .
ds1231/s 3 of 9 power monitor block diagram figure 1 power-up reset figure 2
ds1231/s 4 of 9 input pin hysteresis figure 3 -20 -35 -50 v tp - 2.3 2.15 2.0 v tp + 2.5 2.5 2.5 note: hysteresis tolerance is 60 mv application with mode pin connected to v cc figure 4 v sense = r2 r2 r1 + x 2.3 v max = - vtp sense v x 5.0 example: v sense = 8 volts at trip point and a maximum voltage of 17.5v with r2 = 10k then 8 = 10k 10k r1 + x 2.3 r1 = 25k note: rst requires a pull-up resister.
ds1231/s 5 of 9 application - mode pin connected to ground when the mode pin is connected to ground, pin 1 is a current source of 30 m a with a v tp + of 2.5 volts. pin 1 is held below the trip point by a switching device like an opto-isolator as shown in figure 6. determination of the sense point has the same criteria as discussed in the previous application. however, determining component values is significantly different. in this mode, the maximum dynamic range of the sense point versus desired trip voltage is primarily determined by the selection of a zener diode. as an example, if the maximum voltage at the sense point is 200v and the desired trip point is 150v, then a zener diode of 150v will approximately set the trip point. this is particularly true if power consumption on the high voltage side of the opto-isolator is not an issue. however, if power consumption is a concern, then it is desirable to make the value of r1 high. as the value of r1 increases, the effect of the led current in the opto-isolator starts to affect the in trip point. this can be seen from the equation shown in figure 6. r1 must also be low enough to allow the opto-isolator to sink the 30 m a of collector current required by pin 1 and still have enough resistance to keep the maximum current through the opto- isolator?s led within data sheet limits. figure 7 illustrates how the ds1231 can be interfaced to the ac power line when the mode pin is grounded. ac voltage monitor with transformer isolation figure 5 note: rst requires a pull-up resister.
ds1231/s 6 of 9 application with mode pin grounded figure 6 voltage sense point (trip value) = vz + ctr ic x r1 ctr = if ic ctr = current transfer ratio vz = zen er voltage example: ctr = 0.2 ic = 30 m a if = 150 m a voltage sense point = 105 and vz = 100 volts then 105 = 100 + 2 . 0 30 x r1 r1 = 33k note: rst requires a pull-up resister. ac voltage monitor with opto-isolation figure 7 note: rst requires a pull-up resister.
ds1231/s 7 of 9 absolute maximum ratings* voltage on v cc pin relative to ground -0.5v to +7.0v voltage on i/o relative to ground -0.5v to v cc + 0.5v operating temperature 0c to 70c operating temperature (industrial version) -40c to +85c storage temperature -55c to +125c soldering temperature 260c for 10 seconds * this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. recommended dc operating conditions (0 c to 70 c) parameter symbol min typ max units notes supply voltage v cc 4.5 5.0 5.5 v 1 input pin 1 v in v cc v 1 dc electrical characteristics (0 c to 70 c; v cc =4.5 to 5.5v) parameter symbol min typ max units notes low level @ rst v ol 0.4 v 1 output voltage @ -500 m a v oh v cc -0.5v v cc -0.1v v 1, 6 input leakage i il -10 +10 m a 2 output current @2.4v i oh 1.0 2.0 ma 5 output current @0.4v i ol 2.0 3.0 ma operating current i cc 0.5 2.0 ma 3 input pin 1 (mode=gnd) i c 15 25 50 m a input pin 1 (mode=v cc ) i c 0.1 m a in trip point (mode=gnd) v tp 1 in trip point (mode=v cc ) v tp see figure 3 1 v cc trip point (tol=gnd) v cctp 4.50 4.62 4.74 v 1 v cc trip point (tol=v cc ) v cctp 4.25 4.37 4.49 v 1 capacitance (t a =25 c) parameter symbol min typ max units notes input capacitance c in 5 pf output capacitance c out 7 pf
ds1231/s 8 of 9 ac electrical characteristics (0 c to 70 c; v cc =5v 10%) parameter symbol min typ max units notes v tp to nmi delay t ipd 1.1 m s v cc slew rate 4.75-4.25v t f 300 m s v cc detect to rst and rst t rpd 100 ns v cc detect to nmi t ipu 200 m s 4 v cc detect to rst and rst t rpu 150 500 1000 ms 4 v cc slew rate 4.25-4.75v t r 0 ns notes: 1. all voltages referenced to ground. 2. v cc = +5.0 volts with outputs open. 3. measured with outputs open. 4. t r = 5 m s. 5. rst is an open drain output and requires a pull-up resister. 6. rst remains within 0.5v of v cc on power-down until v cc drops below 2.0v. rst remains within 0.5v of gnd on power-down until v cc drops below 2.0v. timing diagram: power-up
ds1231/s 9 of 9 timing diagram: power-down
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